Serially-accessed type memory device for providing an interleaved data read operation

ABSTRACT

In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

This application is a continuation of application Ser. No. 07/066,260,filed Jun. 25, 1987 now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a memory device and, more particularly,to a memory device used in a memory having a serial access function inthe column direction (i.e., the next access address is determined).

In a conventional random access memory, a series of operations areperformed in one cycle which is determined in accordance with controlsignals or address signals of an external input. These operationsinclude accepting and decoding an externally input address in a columndirection, activation of a column selection line to transfer data to adata bus line, and activation of an output driver to output the data.

On the other hand, in a memory having a serial access function, anaddress to be accessed next is determined, unlike in the random accessmemory. For this reason, the above series of operations need not beperformed in one cycle determined by the externally input signals, butcan be set up (prepared) beforehand.

However, in the arrangement where only one data transmission system isprovided, the above series of operations must be performed by a singledata transfer system, regardless of an operation state from which anaccess in a present cycle is started. For this reason, although anaccess itself can be performed at a high speed, it is difficult toreduce a cycle time.

SUMMARY OF THE INVENTION

The present invention has been made in consideration of the abovesituation, and has as its object to provide a memory device having acolumn-direction serial access function, which is capable of reducing acycle time that cannot be realized by conventional technique.

According to the present invention, in a memory having acolumn-direction serial access function, two or more circuit systems forselecting/fetching data are provided in a single device, and one systemis set up while the other is in an access operation, to thereby reduce acycle time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an essential part of a read section usedwhen the present invention is applied to a serially-accessed typesemiconductor memory;

FIGS. 2A to 2D are flow charts for explaining a data read operation ofthe memory shown in FIG. 1;

FIG. 3 is a block diagram of hardware for alternately operating two datatransfer systems (A and B) in the arrangement shown in FIG. 1;

FIGS. 4A to 4C are views of waveforms for explaining an operation of thehardware shown in FIG. 3;

FIG. 5 is a block diagram of a modification of the hardware shown inFIG. 3, in which data bus switchers (38 and 39) are replaced withregisters (380 and 390);

FIGS. 6A and 6B are flow charts for explaining an operation of thememory shown in FIG. 1 using the hardware shown in FIG. 5;

FIG. 7 is a block diagram of a modification of the hardware shown inFIG. 3, showing hardware capable of reducing a cycle time of the memoryshown in FIG. 1 shorter than that obtained by the hardware shown in FIG.3;

FIG. 8 is a flow chart for explaining an operation of the memory shownin FIG. 1 using the hardware shown in FIG. 7;

FIG. 9 is a block diagram partially showing a changed portion used whenthe arrangement shown in FIG. 1 is applied for data writing; and

FIGS. 10A to 10D are flow charts for explaining a data write operationused when the arrangement shown in FIG. 9 is applied to the memory shownin FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will now be described withreference to the accompanying drawings. FIG. 1 is a block diagram of aninternal circuit arrangement of a column-direction serially-accessedmemory according to the embodiment of the present invention, and FIGS.2A to 2D are flow charts for explaining an operation thereof. Accordingto this embodiment, in a semiconductor memory having a column-directionserial access function, two systems A and B for selecting/fetching dataare provided in a single chip. Reference numerals 20 and 22 denote Adata registers (or A bit lines); 21 and 23, B data registers (or B bitlines); 24 and 26, A column selecting gates; 25 and 27, B columnselecting gates; 28 and 30, A column selecting line drivers; 29 and 31,B column selecting line drivers; 32 and 34, A decoders; 33 and 35, Bdecoders; 36, an A serial address generator; 37, a B serial addressgenerator; 38, an A data bus switcher; 39, a B data bus switcher; 40, anoutput driver; CA0 and CA1, A column selecting lines; CB0 and CB1, Bcolumn selecting lines; DBA and DBA, A data bus lines; DBB and DBB, Bdata bus lines; AA, an A address bus line; AB, a B address bus line; andSO, a data output. All of these circuit elements can be formed in aone-chip IC pellet.

A data read operation of the memory shown in FIG. 1 will be described.Assume that registers (or bit lines) 20, 21, 22, and 23 are accessed inthis order. Note that a description will be made with reference to acase wherein the present cycle is a cycle for accessing data of register22 which belongs to system A.

In this case, since the preceding cycle is a cycle for accessing fromsystem B, switcher 38 is turned off, as shown in step ST1 of FIG. 2B,and switcher 39 is activated and hence is in an ON state, as shown instep ST11 of FIG. 2C. As shown in steps ST12 and ST13, data of register21 are transferred to driver 40 through bus lines DBB and DBB.

On the other hand, when system A is disconnected from driver 40 by OFFswitcher 38, an address of the present cycle is set in generator 36(step ST2), and decoder 34 corresponding to the set address is selected(step ST3). Then, selecting line CA1 is activated (step ST4), and dataof register 22 are transferred to bus lines DBA and DBA, as shown instep ST5.

When a present cycle, subsequent to the above cycle, begins (FIG. 2A),switcher 39 is turned off as shown in step ST31 of FIG. 2C, and switcher38 is activated and hence is in an ON state as shown in step ST21 ofFIG. 2B. Then, bus lines DBA and DBA are connected to driver 40 throughON switcher 38 (step ST22). The data of register 22 is transferred todriver 40 as shown in step ST23, and data SO transferred from driver 40is output.

When system B is disconnected from driver 40, generator 37 is activated,and the address is counted up (or down) as shown in step ST32. Decoder35 is selected in correspondence to the counted-up (or -down) address(step ST33), and selecting line CB1 is activated (step ST34). Then, thedata of register 23 are transferred to bus lines DBB and DBB as shown instep ST35, thereby completing set-up for access in the next cycle.

FIG. 3 shows hardware for alternately operating systems A and B in thearrangement shown in FIG. 1. FIGS. 4A to 4C show waveforms forexplaining an operation of the hardware shown in FIG. 3.

External clock SC (FIG. 4A) having a period of one cycle shown in FIG.2A is converted through 1/2 frequency divider 41 into pulse φA (FIG. 4B)for selecting system A. Pulse φA is supplied to a 3-state buffer whichconstitutes switcher 38. When pulse φA is logic "1", buffer 38 connectsbus lines DBA and DBA to driver 40. When pulse φA is logic "0", buffer38 is opened, and bus lines DBA and DBA are disconnected from driver 40.

Pulse φA is phase-inverted, via inverter 42, to be a synchronous signalhaving the same waveform as that of pulse φB of FIG. 4C, and is suppliedto a clock input terminal of an address counter in generator 36. Acontent (address data) of output AA of generator 36 is updated (countedup or down) by 1 at the fall timing of pulse φA.

In addition, pulse φA is phase-inverted, by inverter 43, to be pulse φBof FIG. 4C. Pulse φB is further phase-inverted, by inverter 44, to be asynchronous signal having the same waveform as that of pulse φA of FIG.4B, and is supplied to a clock input terminal of an address counter ingenerator 37. A content (address data) of output AB of generator 37 isupdated (counted up or down) by 1 at the fall timing of pulse φB.

On the other hand, In order to select system B, pulse φB is supplied toa 3-state buffer which constitutes switcher 39. When pulse φB is logic"1", buffer 39 connects bus lines DBB and DBB to driver 40. (At thistime, since pulse φA is logic "0", driver 40 is disconnected from buslines DBA and DBA.)

As described above, switchers 38 and 39 are alternately opened/closedevery one period (one cycle of FIG. 2A) of clock SC so as to alternatelyselect systems A and B. Then, in synchronism with each alternateselection, the contents of data AA and AB are updated by 1 for every twoperiods (two cycle of FIG. 2A) of clock SC.

FIG. 5 shows hardware wherein switchers 38 and 39 shown in FIG. 3 arereplaced with registers/switches 380 and 390, respectively. When thehardware shown in FIG. 3 is used, systems A and B are alternatelyswitched in the order of A→B→A→B→. . . However, when the hardware shownin FIG. 5 is used, the same data can be alternately switched twice as inthe order of A→A B→B→A→A→B→B→. . . This two-time alternate switchingoperation is exemplified in FIGS. 6A and 6B.

When the above two-time alternate switching operation is to beperformed, 1/2 frequency divider 381 is inserted between frequencydivider 41 and each of registers/switchers 380 and 390, in order thatthe connections for registers/switchers 380 and 390 are alternativelyswitched for each two cycles. More specifically, frequency-dividedoutput φN from divider 381 is applied to register/switcher 380, and thephase-inverted signal of output φN, obtained via inverter 43, is appliedto register/switcher 390. In this circuit configuration, output signalφN from divider 381 has a period two times longer than the period ofclock φA.

In the A system, the data transmission from bus lines DBA, DBA toregister 380 is carried out at the timing of the falling edge ofexternal control clock input SC, provided φN=logic "1". After completionof the data transmission, register 380 is disconnected from bus linesDBA, DBA. Meanwhile, during the period of φN=logic "1", register 380 isconnected to output driver 40.

In the B system, the data transmission from bus lines DBB, DBB toregister 390 is carried out at the timing of the falling edge ofexternal control clock input SC, provided φN=logic "0". After completionof the data transmission, register 390 is disconnected from bus linesDBB, DBB. Meanwhile, during the period of φN=logic "0", register 390 isconnected to output driver 40.

In the embodiment of FIG. 5, the contents of address AA (or AB) arerequired to be fixed during the two-time transmission of the same dataDBA (or DBB). To satisfy this requirement, 1/2 frequency divider 361 isinserted between frequency divider 41 and each of address generators 36and 37. More specifically, frequency-divided output φA from divider 41is applied to frequency divider 361 via inverter 42. Frequency-dividedoutput φN' from divider 361 is applied to address generator 36, and isapplied, via inverter 44, to address generator 37. Note here that outputφN' from divider 361 is to be activated one cycle in advance of theactivation of output φN from divider 381.

According to the embodiment of FIG. 5, when 1/N (N is a natural number)frequency dividers are used both for dividers 361 and 381, an N-timealternate switching operation can be performed.

When the same data is transferred a plurality of times as shown in FIG.5, reliability of a content of the transferred data can be improved.However, since an operation speed of the memory is reduced, the hardwareshown in FIG. 5 may be adopted as necessary.

FIG. 7 shows a modification of switchers 38 and 39 shown in FIG. 3.According to the modification shown in FIG. 7, switcher 38a (3-statebuffer) is conducted by an output of logic "1" from inverter 45 whileswitcher 38c (3-state buffer) is opened by logic "0" of pulse φA,thereby storing the data of bus lines DBA and DBA in register 38b.

While the data of system A is stored, switcher 38c conducted by logic"1" of pulse φB, and a content of register 39b is supplied to buffer 40.At this time, since an output from inverter 46 is logic "0", switcher39a is opened.

When φA=logic "1" and φB=logic "0" in the next cycle, a content ofregister 38b is supplied to driver 40, and at the same time, the data ofbus lines DBB and DBB are stored in register 39b.

FIG. 8 shows an operation of the modification shown in FIG. 7. As willbe seen from a comparison of the flow chart shown in FIG. 8 with thoseshown in FIGS. 2B and 2C, a time required for one cycle is reduced bythe arrangement shown in FIG. 7. That is, five steps ST1 to ST5 in onecycle of FIG. 2B are reduced to three serial steps in FIG. 8 when viewedalong the serial flow of time. Similarly, five serial steps ST31 to ST35in FIG. 2C are reduced to three serial steps in FIG. 8. Thus, the numberof processing steps, included time-serially in one cycle, is reduced, sothat a cycle time can be reduced more effectively.

FIG. 9 shows a modified portion when the arrangement (for reading outdata) shown in FIG. 1 is modified to that for writing data. Writinginput data SI is converted into data DB in phase with data SI and dataDB opposite phase to data SI through input buffer 400. Data DB and DBare supplied to bus lines DBA and DBA through data bus switcher 386, andare supplied to bus lines DBB and DBB through switcher 396. The otherportions of the arrangement of FIG. 9 can be the same as those of thearrangement shown in FIG. 1. FIGS. 10A and 10B show a data writeoperation of the arrangement, obtained by applying the modified portionshown in FIG. 9 to the arrangement shown in FIG. 1.

According to the embodiments as shown in FIG. 1 etc., systems A and Bare operated with a time shift of about 1/2 cycle. For this reason, onecycle time of these embodiments only requires a time substantially halfthat of a conventional one cycle including steps ST1 to ST5 and ST21 toST23. Therefore, a cycle time can be reduced. That is, according to thepresent invention, both the systems (A, B) are alternately operated sothat data is set up in one system (e.g., A) while data is output in theother (e.g., B), thereby reducing the cycle time. In addition, when thepresent invention is applied in a single semiconductor memory chip andtwo systems (A and B) of data selecting/fetching circuits are providedtherein, a high speed memory operation can be achieved by the singlechip.

Note that the present invention can be applied to all the memoriesexcept a random access type (i.e., wherein an address to be accessednext to the present address is determined). Therefore, the presentinvention can also be applied to reduction in a read cycle time of aserially-accessed type semiconductor ROM or of a CDROM havingtwo-channel optical pickup systems, etc.

What is claimed is:
 1. A semiconductor memory having a column-directionserial access function with odd and even read operation cycles,comprising:frequency divider means for providing a plurality of clocksignals to distinguish between odd and even read operation cycles; firstserial address generator means for generating first address data; secondserial address generator means for generating second address data; firstdecoder means for decoding the first address data to provide a firstplurality of selection signals; second decoder means for decoding thesecond address data to provide a second plurality of selection signals;first bus means for transferring read data that is output during oddoperation cycles; second bus means for transferring read data that isoutput during even operation cycles; a first plurality of registers forstoring read data that is output during odd read operation cycles; asecond plurality of registers for storing read data that is outputduring even read operation cycles; output means for outputting readdata; first column selection gate means, coupled to the first bus meansand to the first plurality of registers, for selectively coupling one ofsaid first plurality of registers to said first bus means in accordancewith the first plurality of selection signals and only at times whenread data is output from the first plurality of registers; second columnselection gate means, coupled to the second bus means and to the secondplurality of registers, for selectively coupling one of said secondplurality of registers to said second bus means in accordance with thesecond plurality of selection signals and only at times when read datais output from the second plurality of registers; odd switcher means,coupled to the first bus means and to the frequency divider means, forcoupling said first bus means to said output means during odd readoperation cycles; and even switcher means, coupled to the second busmeans and to the frequency divider means, for coupling said second busmeans to said output means during even read operation cycles.
 2. Asemiconductor memory in accordance with claim 1, in which:the firstdecoder means includes means for providing a first and a secondselection signal; the second decoder means includes means for providinga third and a fourth selection signal; the first plurality of registersincludes a first and a second register; the second plurality ofregisters includes a third and a fourth register; the first columnselection gate means includes means for coupling the first register tothe first bus means in accordance with the first selection signal, andincludes means for coupling the second register to the first bus meansin accordance with the second selection signal; the second columnselection gate means includes means for coupling the third register tothe second bus means in accordance with the third selection signal, andincludes means for coupling the fourth register to the second bus meansin accordance with the fourth selection signal.
 3. A semiconductormemory in accordance with claim 2, in which the semiconductor memorycomprises a single integrated circuit.
 4. A semiconductor memory inaccordance with claim 2, in which:the first bus means and odd switchermeans include first latch means, for temporarily storing read data fromthe first bus means and transferring the stored read data to the outputmeans during odd read operation cycles; and the second bus means andeven switcher means include second latch means, for temporarily storingread data from the second bus means and transferring the stored readdata to the output means during even read operation cycles.
 5. Asemiconductor memory in accordance with claim 2, in which:the oddswitcher means includes means for coupling said first bus means to saidoutput means for a time period corresponding to a plurality of odd readoperation cycles; and the even switcher means includes means forcoupling said second bus means to said output means for a time periodcorresponding to a plurality of even read operation cycles.
 6. Asemiconductor memory in accordance with claim 1, in which thesemiconductor memory comprises a single integrated circuit.
 7. Asemiconductor memory in accordance with claim 1, in which:the first busmeans and odd switcher means include first latch means, for temporarilystoring read data from the first bus means and transferring the storedread data to the output means during odd read operation cycles; and thesecond bus means and even switcher means include second latch means, fortemporarily storing read data from the second bus means and transferringthe stored read data to the output means during even read operationcycles.
 8. A semiconductor memory in accordance with claim 1, inwhich:the odd switcher means includes means for coupling said first busmeans to said output means for a timer period corresponding to aplurality of odd read operation cycles; and the even switcher meansincludes means for coupling said second bus means to said output meansfor a time period corresponding to a plurality of even read operationcycles.